The invention relates to an address buffer in MOS technology with an address memory circuit exhibiting an address input, a control input for a transfer signal, two complementary address outputs, and two complementary signal outputs of high signal level. The address buffer also has an isolation amplifier and a following-connected output stage.
Address buffers for MOS memory modules generally consist of three parts, namely, an address memory circuit, a following-connected isolating amplifier, and a following output stage. Accordingly, the address memory circuit has the job of pre-amplifying up to the MOS level the TTL address signals and to take them over. The complementary address output signals A and A as well as the allocated high voltage signals with a maximum potential of one and one half times the operating voltage C and C can be tapped at its output.
The following-connected isolating amplifiers function as intermediate amplifiers and separate the outputs of the address memory circuit, which can be only slightly loaded, from the output stages. Therefore, these blocking preliminary stages supply the complementary control signals CV and CV which both have an idle level of 0 volts.
The isolating amplifiers themselves are connected with the output stages which only represent power amplifiers which supply the complementary address signals AA and AA to the decoders via the address line.
In order to prevent multiple or erroneous selection in the decoders, it is necessary that the outputs of the output stages which are driven if necessary with the information "0", exhibit no voltage peaks or residual voltages that are greater than an allocated threshold voltage.
Known address buffers (Intel memory module 2104 and 2107) only exhibit output stages without isolating amplifiers in addition to the address memory circuit. Therefore, it is a matter of pure push-pull output stages which are driven by the address outputs A and A of the address memory circuit. These output stages are not activated by means of a special start clock pulse but rather by means of the transfer clock pulse of the address memory circuit. Although this technique has the advantage that one obtains the address output signals AA and AA of the output stage very early, great voltage peaks occur, however, at the output driven under certain conditions with the zero information signal. The size of these disturbing voltages can only be limited by means of an appropriate choice of the output stage transistors, which in turn leads to significant cross-currents in the output stages, whereby these output stage transistors must be dimensioned very large.
In another known address buffer (Mostek memory module MK4027 and MK4116) output stages with blocking preliminary stages are provided. Here, the isolating amplifiers consist of a static flip-flop whose load transistors are driven by means of the high voltage signals C and C of the address memory circuit. Here, too, voltage peaks can occur at the outputs of the blocking preliminary stages CV or respectively CV when the information "0" is to be supplied.
The output stage employed in the known address buffer is a simple source follower which has the undesired property of also boosting the outputs of the output stage AA or, respectively AA when they are only driven with short disturbing voltage peaks.